secret_amd64.s

Documentation: runtime

     1// Copyright 2024 The Go Authors. All rights reserved.
     2// Use of this source code is governed by a BSD-style
     3// license that can be found in the LICENSE file.
     4
     5#include "go_asm.h"
     6#include "textflag.h"
     7#include "funcdata.h"
     8
     9// TODO(dmo): generate these with mkpreempt.go, the register sets
    10// are tightly coupled and this will ensure that we keep them
    11// all synchronized
    12
    13// secretEraseRegisters erases any register that may
    14// have been used with user code within a secret.Do function.
    15// This is roughly the general purpose and floating point
    16// registers, barring any reserved registers and registers generally
    17// considered architectural (amd64 segment registers, arm64 exception registers)
    18TEXT ·secretEraseRegisters(SB),NOFRAME|NOSPLIT,$0-0
    19	XORL	AX, AX
    20	JMP ·secretEraseRegistersMcall(SB)
    21
    22// Mcall requires an argument in AX. This function
    23// excludes that register from being cleared
    24TEXT ·secretEraseRegistersMcall(SB),NOSPLIT|NOFRAME,$0-0
    25	// integer registers
    26	XORL	BX, BX
    27	XORL	CX, CX
    28	XORL	DX, DX
    29	XORL	DI, DI
    30	XORL	SI, SI
    31	// BP = frame pointer
    32	// SP = stack pointer
    33	XORL	R8, R8
    34	XORL	R9, R9
    35	XORL	R10, R10
    36	XORL	R11, R11
    37	XORL	R12, R12
    38	XORL	R13, R13
    39	// R14 = G register
    40	XORL	R15, R15
    41
    42	// floating-point registers
    43	CMPB	internal∕cpu·X86+const_offsetX86HasAVX(SB), $1
    44	JEQ	avx
    45
    46	PXOR	X0, X0
    47	PXOR	X1, X1
    48	PXOR	X2, X2
    49	PXOR	X3, X3
    50	PXOR	X4, X4
    51	PXOR	X5, X5
    52	PXOR	X6, X6
    53	PXOR	X7, X7
    54	PXOR	X8, X8
    55	PXOR	X9, X9
    56	PXOR	X10, X10
    57	PXOR	X11, X11
    58	PXOR	X12, X12
    59	PXOR	X13, X13
    60	PXOR	X14, X14
    61	PXOR	X15, X15
    62	JMP	noavx512
    63
    64avx:
    65	// VZEROALL zeroes all of the X0-X15 registers, no matter how wide.
    66	// That includes Y0-Y15 (256-bit avx) and Z0-Z15 (512-bit avx512).
    67	VZEROALL
    68
    69	// Clear all the avx512 state.
    70	CMPB	internal∕cpu·X86+const_offsetX86HasAVX512(SB), $1
    71	JNE	noavx512
    72
    73	// Zero X16-X31
    74	// Note that VZEROALL above already cleared Z0-Z15.
    75	VMOVAPD	Z0, Z16
    76	VMOVAPD	Z0, Z17
    77	VMOVAPD	Z0, Z18
    78	VMOVAPD	Z0, Z19
    79	VMOVAPD	Z0, Z20
    80	VMOVAPD	Z0, Z21
    81	VMOVAPD	Z0, Z22
    82	VMOVAPD	Z0, Z23
    83	VMOVAPD	Z0, Z24
    84	VMOVAPD	Z0, Z25
    85	VMOVAPD	Z0, Z26
    86	VMOVAPD	Z0, Z27
    87	VMOVAPD	Z0, Z28
    88	VMOVAPD	Z0, Z29
    89	VMOVAPD	Z0, Z30
    90	VMOVAPD	Z0, Z31
    91
    92	// Zero k0-k7
    93	KXORQ	K0, K0, K0
    94	KXORQ	K0, K0, K1
    95	KXORQ	K0, K0, K2
    96	KXORQ	K0, K0, K3
    97	KXORQ	K0, K0, K4
    98	KXORQ	K0, K0, K5
    99	KXORQ	K0, K0, K6
   100	KXORQ	K0, K0, K7
   101
   102noavx512:
   103	// misc registers
   104	CMPL	BX, BX	//eflags
   105	// segment registers? Direction flag? Both seem overkill.
   106
   107	RET
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